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TDA7535 DELTA/SIGMA CASCADE 20 BIT STEREO DAC 20-bit resolution single ended output Analog reconstruction third order Chebyshev filter I2S input data format On chip PLL System clock: 64 Fs 2 output channels 0.9 VRMS single ended output dynamic 3.3V power supply Reset Sampling rate 36KHz to 48KHz SO14 ORDERING NUMBER: TDA7535 DESCRIPTION The TDA7535 is a stereo, digital-to-analog converter designed for audio application, including digital interpolation filter, a third order multibit Delta-Sigma DAC, a third order Chebyshev's reconstruction filter and a differential to single ended output converter. This device is fabricated in highly advanced CMOS, where high speed precision analog circuits are combined with high density logic circuits. The TDA7535, according to standard audio converters, can accept any I2S data format. BLOCK DIAGRAM The TDA7535 is available in SO14 package. The total power consumption is less than 75mW. TDA7535 is suitable for a wide variety of applications where high performance are required. Its low cost and single 3.3V power supply make it ideal for several applications, such as CD players, MPEG audio, MIDI applications, CD-ROM drives, CD-Interactive, digital radio applications and so on. An evaluation board is available to perform measurement and to make listening tests. I2 S I 2S DIGITAL INPUT 20 FS CLKOUT FIR1 FIR2 FIR3 20 8FS S&H 23 64FS MODULATOR PLL ALU 4 ANALOG OUTPUT THERMO DECODER & RANDOMIZER D02AU1417 3rd CHEBYSHEV SC FILTER DIFF TO SINGLE CONVERTER Rev. 7 February 2006 1/9 TDA7535 ABSOLUTE MAXIMUM RATINGS Symbol VDD VCC Vaio Vdio Vdi5 Tj Tstg Power supplies Analog Input and Output Voltage Digital Input and Output Voltage Digital Input Voltage (5V tolerant) Operating Junction Temperature Range Storage Temperature Parameter Digital Analog Value -0.5 to +4.6 -0.5 to +4.6 -0.5 to (VCC+0.5) -0.5 to (VDD+0.5) -0.5 to 6.5 -40 to 125 -55 to 150 Unit V V V V V C C Warning: Operation at or beyond these limit may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. THERMAL DATA Symbol Rth j-amb Parameter Thermal resistance junction to ambient (1) Value 85 Unit C/W Note: 1. In still air PIN CONNECTIONS (Top view) N.C. SDATA SCK N.C. GND_DIG GND_ANA OUTSR 1 2 3 4 5 6 7 D01AU1276A 14 13 12 11 10 9 8 RESETN FSYNC VDD_DIG N.C. VDD_ANA VCM OUTSL PIN FUNCTION Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Pin Name N.C. SDATA SCK N.C. GND_DIG GND_ANA OUTSR OUTSL VCM VDD_ANA N.C. VDD_DIG FSYNC RESETN Input/Output Power I I P P O O P P P I I I2S Digital Data Input I2S Clock Input Digital Ground Analog Ground Right Channel single ended Output Left Channel single ended Output Reference 1.65V externally filtered Analog 3.3V-Supply Digital 3.3V-Supply I2S Left-Right Channel selector Reset (active low) Description 2/9 TDA7535 RECOMMENDED DC OPERATING CONDITIONS Symbol VDD VCC Parameter 3.3V Digital Power Supply Voltage 3.3V Analog Power Supply Voltage Test Condition Min. 3.15 3.15 Typ. 3.3 3.3 Max. 3.45 3.45 Unit V V POWER CONSUMPTION Symbol Idd Parameter Total Maximum Current Test Condition power supply @ 3.3V and Tj = 125C Min. Typ. 21.5 Max. 25 Unit mA GENERAL INTERFACE ELECTRICAL CHARACTERISTICS Symbol lil lih Ilatchup Vesd Parameter Low Level Input Current without pullup device High Level Input Current without pullup device I/O latch-up current Electrostatic Protection Test Condition Vi = 0V (note 1) Vi = Vdd (note 1) V < 0V, V > Vdd Leakage , 1A (note 2) 200 2000 Min. Typ. Max. 1 1 Unit A A mA V Note: 1. The leakage currents are generally very small, <1nA. The value given here, 1mA, is the maximum that can occur after an Electrostatic Stress on the pin. 2. Human Body Model. LOW VOLTAGE CMOS INTERFACE DC ELECTRICAL CHARACTERISTICS Symbol Vil Vih Vhyst Parameter Low Level Input Voltage High Level Input Voltage Schmitt trigger hysteresis 0.8*Vdd 0.8 Test Condition Min. Typ. Max. 0.2*Vdd Unit V V V DAC ELECTRICAL CHARACTERISTICS Vdd = 3.3V; Tamb = 25C; Input signal frequency = sinus wave generated by Audio Precision Sys.2; Input Signal Amplitude = see notes; Noise Integration Bandwidth = 20Hz to 22KHz (A- weighted) Parameter Noise + Distortion (see note 1) Test Condition @0dB @-6dBb @-40dB @-60dB see note 2 see note 3 see note 4 Vdd = 3.15 to 3.45V Full scale input 0.8 36 0.12 70(5) 84(6) Min. Typ. 89 94 96 96 94 96 -95 0.9 1.0 48 Max. Unit dB dB dB dB dB dB dB Vrms kHz dB Total Harmonic Distortion Dynamic range Crosstalk Full Scale Output Voltage Input Sampling Rate Passband Ripple 3/9 TDA7535 DAC ELECTRICAL CHARACTERISTICS (continued) Vdd = 3.3V; Tamb = 25C; Input signal frequency = sinus wave generated by Audio Precision Sys.2; Input Signal Amplitude = see notes; Noise Integration Bandwidth = 20Hz to 22KHz (A- weighted) Parameter Stopband Test Condition @ 3dB @ 90dB 44.1kHz Sampling Rate Min. 21.53 24.80 0.05 0.1 dB Typ. Max. Unit kHz Interchannel Gain Mismatch Note1: Note 2: Note 3: Note 4: Note 5 Note 6 It is the ratio between the maximum input signal and the integration of the in-band noise after deducing the power of signal fundamental. It depends on the input signal amplitude. In this case 0dB means full scale digital, 1kHz frequency used. It is the ratio of the rms value of the signal fundamental component at 0dB (full scale digital) to the rms value of all of the harmonic components in the band. measured using the SNR at -60dB input signal, with 60dB added to compensate for small input signal. Left channel on with 0dB/1kHz input signal, Right channel on with DC input signal. by correlation to beuch results. ATE limits are 60dB by correlation to beuch results. ATE limits are 80dB Figure 1. I2S interface Diagram Left FSYNC Right 32 * SCK SCK SDATA 32 * SCK 20 Bits 20 Bits MSB LSB MSB LSB 4/9 TDA7535 Figure 2. I2S Timings SDATA Valid FSYNC tsckr Valid tsckf SCK tlrwtlrw+ tsds tsckpl tsck tsdh tsckph Timing tsck tsckpl tsckph tlrwtlrw+ tsds tsdh tsckr tsckf Clock Cycle(1) SCK Phase Low SCK Phase High Description Minimum 1/(64*Fs) 150psRMS 0.5*tsck - 1% 0.5*tsck - 1% 0 0 60 30 Maximum 1/(64*Fs) + 150psRMS 0.5*tsck +1% 0.5*tsck +1% 0.125*tsck-10 0.125*tsck-10 Unit ns ns ns ns ns ns ns FSYNC switching time window before SCK falling edge(2) FSYNC switching time window after SCK falling edge(2) SDATA setup time SDATA hold time SCK rise time SCK fall time 22 20 ns ns (1) SCK clock defines the Fs, being the Sample Rate. This input clock needs a jitter below ~212psRMS (2) FSYNC switches inside the time window as specified w.r.t. to falling edge of SCK Figure 3. Power Up & Reset Sequence VDD RESET TRES TRES Min 50ms D02AU1418 5/9 TDA7535 Figure 4. Frequency response Figure 5. R2 10K +3.3 VDIG C7 10F 10V 14 SW1 P +3.3VANA 10F RESETN 10 VDD_ANA 10H bead inductor VDD_DIG 100nF(*) 100nF(*) TP1 SDATA TP2 2 IS U4 2 SCK TP3 FSYNC 3 12 13 10F TP5 GND_DIG 5 8 OUTSL TP6 6 TP7 9 7 OUTSR TP8 D02AU1419B (*) AS CLOSE AS POSSIBLE TO THE PIN J3 BNC OUTSL GND_ANA VCM C16 100nF (*) C15 47F 10V (*) J4 BNC OUTSR 6/9 TDA7535 Figure 6. SO14 Mechanical Data & Package Dimensions mm DIM. MIN. A A1 A2 B C D (1) E e H h L k ddd 5.8 0.25 0.40 1.35 0.10 1.10 0.33 0.19 8.55 3.80 1.27 6.20 0.50 1.27 0.228 0.01 0.016 TYP. MAX. 1.75 0.30 1.65 0.51 0.25 8.75 4.0 MIN. 0.053 0.004 0.043 0.013 0.007 0.337 0.150 0.050 0.244 0.02 0.050 TYP. MAX. 0.069 0.012 0.065 0.020 0.01 0.344 0.157 inch OUTLINE AND MECHANICAL DATA 0 (min.), 8 (max.) 0.10 0.004 (1) "D" dimension does not include mold flash, protusions or gate burrs. Mold flash, protusions or gate burrs shall not exceed 0.15mm per side. SO14 0016019 D 7/9 TDA7535 REVISION HISTORY Date December 2003 December 2005 February 2006 Revision 5 6 7 Initial release in EDOCS. Update Electrical Characteristics. Add Revision History Updated max. value of tsckr and tsckt parameter on page 5/9. Changes 8/9 TDA7535 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2006 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 9/9 |
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